Such converters generally use a network of identical resistors R in series supplied with a constant current I0 so as to produce the reference voltages distributed at regular intervals of value Vtap=R·I0, and N differential amplifiers each associated with a respective reference voltage so as to determine whether the input voltage is greater or less than this reference voltage or to linearly amplify the disparity between the input voltage and this reference voltage. The junction points of the resistors constitute intermediate taps connected to the inputs of the amplifiers.
The simplest structure is that which is represented in FIG. 1 depicting a network of resistors in series R1 to RN traversed by a fixed current I0 and a set of differential amplifiers or comparators A1 to AN, the amplifier Aj of rank j receiving on the one hand the voltage Vin to be converted, and on the other hand the voltage at the junction point of resistor Rj+1 and resistor Rj.
This structure can be used for a final analog-digital conversion stage, the amplifiers toggling in one direction or the other depending on the direction of the difference between the input voltage and the reference voltage. It can also be used as input stage or intermediate analog-digital conversion stage, followed by other conversion stages, and in this case each amplifier must provide, destined for the following stages, a voltage or a current varying linearly as a function of the difference between the input voltage Vin and the reference voltage associated with this amplifier.
It is desired to be able to make converters having ever greater linearity so as to be able to perform precise conversions with ever higher resolution. It is sought for example to make converters with 12 or 14 bit resolution. The linearity errors are due to the imperfections of the resistors which may have values that are not entirely identical; they are due also to the fact that even if the resistors are identical, the inputs of the amplifiers divert a part of the current which crosses the resistors so that the currents traversing the resistors on the top of the series are higher than the currents traversing the resistors on the bottom of the series. FIG. 1 schematically represents an input current Ib diverted onto each amplifier input connected to the network of resistors. This current Ib is in practice the base current of a bipolar input transistor of the amplifier. It follows from this that the potentials of the intermediate taps of the series network of resistors are not regularly distributed with voltage intervals R·I0 between two successive intermediate taps of the series of resistors. It may be reckoned that the overall non-linearity error is proportional to the square of the number N of amplifiers, to the value of the elementary resistance R, and to the value of the input current Ib consumed by each amplifier.
It is not possible to decrease R beyond certain limits for reasons of manufacturing precision and current consumption. The number N depends on the resolution desired for the stage, for example N=64 for 6 bits. A minimum current Ib is imposed by the dynamic performance of the differential amplifiers which must be able to work at high speed. It would be possible to use MOS technologies with low input current consumption but with these technologies it is difficult to achieve sufficient manufacturing precision to obtain the performance afforded by bipolar technologies.
Solutions involving current compensation have already been devised, wherein currents of value Ib are injected into the intermediate taps of the ladder of resistors so as to neutralize the loss of current Ib to the amplifiers. These solutions are complex and very sensitive to temperature variations or to dispersion in the technological manufacturing parameters; this is because the problem is to compensate a base current which is directly related to the gain in current β of the input transistor of the differential stage, but the value of the current gain is highly dispersed and variable with temperature.
Inspiration could possibly be drawn from the differential structure described in patent application WO 2005/055431, which was devised for increasing the speed performance of converters. This structure, recalled in FIG. 2, uses differential amplifiers A1 to AN with four inputs each; the amplifier Aj of rank j receives on the one hand on two first inputs the differential voltage to be converted Vep−Ven, and on the other hand on two other inputs the voltages sampled from two symmetric taps, of rank j and N−j+1 respectively, of the network of resistors in series. Thus, the first amplifier A1 is linked to the first intermediate tap P1 and to the last PN, the second is linked to the second tap P2 and to the penultimate PN−2, etc. With this structure, it would be possible to solve the problem engendered by this current Ib diverted from each tap of the network of resistors, on account of the symmetry of the structure which establishes a natural compensation for this current. Indeed, what counts in this structure is not the linearity of distribution of the potentials of the taps P1 to PN, it is the linearity of the succession of potential differences between taps Pj and PN−j+1 when j increases from 1 to N. Now, whatever j, the voltage drop between the taps Pj and PN−j+1 results from the addition of voltage drops in the resistors at the top of the set, traversed by bigger currents, and of voltage drops in the resistors at the bottom, traversed by smaller currents, so that on average the distribution of the voltage drops remains regular, even if the mean current in the resistors is not I0 as would be desired but rather I0+N·Ib.
Nevertheless, this compensation takes place only on condition that the current Ib is independent of the input voltage Vep−Ven to be converted. But this is not the case. It would be possible to contrive matters so that this is the case by inserting a follower stage between each tap of the network and the input of the corresponding differential amplifier; but this would introduce additional problems of matching of circuits, of dispersion as a function of temperature, of additional current consumption, of noise introduced by the follower stage, and of additional base-emitter voltage drop which is harmful if it is desired to work with a power supply at very low voltage such as 3.3 volts.
By way of example, a linearity error calculation simulation in the configuration of FIG. 2, for a 14-bit converter whose first stage comprises 80 differential amplifiers, leads to the conclusion that the integral non-linearity error over the conversion ladder may attain 7.5 LSB (least significant bits) in an example where the supply current to the network of resistors is 30 milliamperes, the differential pairs of the amplifiers have current supplies of 200 microamperes, and the mean base current is 1.7 microamperes. The integral non-linearity error INL is the aggregate sum of the differences between the theoretical values of the reference voltages and their actual values. These 7.5 least significant bits represent too big an error, which it is desired to reduce.
It has been noted that if the network of resistors of FIG. 2 was supplied between two reference voltage sources rather than between a high voltage source and a low current source, the integral non-linearity error was divided in a ratio of almost 2.5, which is considerable. Under the same measurement conditions, this leads to an integral non-linearity error of 3 LSB peak to peak for a 14-bit converter, which is much more satisfactory. Power supply through two reference voltages therefore improves performance.
Attempts have also been made to verify whether it was possible to further improve the integral non-linearity of the structure by using a double ladder of resistors in series supplied between two reference voltages, instead of a simple ladder supplied between two reference voltages; one of the inputs of the amplifier is then tapped on a tap of rank j of one of the ladders while the other input is tapped on a tap of rank N−j+1 of the other ladder. But the result is not conclusive since the same conditions as above lead to an integral non-linearity of 4.7 LSB. The double ladder of resistors is therefore useless from the point of view of the integral non-linearity since it impairs performance.